1. Field of the Invention
The present invention generally relates to a display driver and a display driving method, and more particularly, to a display driver and a display driving method for selectively processing gray-level compensation of data synchronized with a write clock.
2. Description of the Related Art
Liquid crystal display (LCD) devices do not properly display fast video data due to a slow response speed of liquid crystal. More particularly, when LCD devices display fast video data, since the response speed of liquid crystal is not greater than a variation speed of display data voltages applied to both ends of a liquid crystal display, LCD devices fail to obtain good video quality. Accordingly, various kinds of over-driving and under-driving technologies for processing gray-level compensation have been suggested. For example, gray-level compensation processing technologies, such as response time acceleration (RTA), dynamic capacitance compensation (DCC), etc., are used by display drivers having a synchronous interface (discussed below) to compare display data of a current frame with display data of a previous frame, to compensate display data voltages according to the comparison results, and to apply the compensated display data voltages to a liquid crystal display to accelerate the response time of the liquid crystal.
Display drivers receive display data and generate display data voltages using a synchronous interface, such as an RGB interface, and an asynchronous interface, such as a central processing unit (CPU) interface.
FIG. 1A is a block diagram illustrating a conventional synchronous interface, and FIG. 1B is a timing diagram of display data DATA and display data voltages V_display illustrated in FIG. 1A.
Referring to FIG. 1A, a CPU, an application processor 110, and a display driver 120 are used in a synchronous interface type. The CPU outputs a control command CMD. The application processor 110 synchronizes the display data DATA with synchronous signals SYNC, such as horizontal synchronous signals HSYNC, vertical synchronous signals VSYNC, data write clock signals DOTCLK and the like, and transmits the synchronized display data DATA to the display driver 120. The display driver 120 generates the synchronized display data voltages V_display based on the display data DATA. The display driver 120 can include a frame memory (not shown) and a gray-level compensator (not shown) to compensate for gray-levels of the display data voltages V_display and output the compensated display data voltages V_display.
Referring to FIG. 1B, the application processor 110 transmits the synchronized display data DATA: A, B, C, D, E and F to the display driver 120 in each frame. The display driver 120 outputs the compensated display data voltages V_display corresponding to the synchronized display data DATA, such that DATA: A is output in frame n frame, DATA: B is output in frame n+1, . . . , and DATA: F is output in an frame n+5.
FIG. 2A is a block diagram illustrating a conventional asynchronous interface type, and FIG. 2B is a timing diagram of display data DATA_write and display data voltages V_display illustrated in FIG. 2A.
Referring to FIG. 2A, a CPU and a display driver 230, including a frame memory 233 and a scan driver 236, are used in the asynchronous interface type. The CPU transmits asynchronous signals ASYNC, such as write indicating signal WRB, data command determination signals RS, etc., and display data DATA to the display driver 230. Asynchronous display data DATA_write is written to the frame memory 233. The display data DATA_write is output as scan data DATA_Scan from the frame memory 233. The scan driver 236 outputs display data voltages V_display corresponding to the scan data DATA_Scan.
Referring to FIG. 2B, the CPU randomly transmits display data DATA_Write: A, B, C and D to the display driver 230 without timing limitations. More particularly, the display data DATA are transmitted from the CPU to the display driver 230 in some frames, but not in other (oblique line) frames. In the frames in which the display data DATA are not transmitted from the CPU to the display driver 230, the scan driver 236 redundantly outputs the display data voltages V_display corresponding to display data stored in the frame memory 233. Therefore, as shown in FIG. 2B, the display driver 230 outputs the display data voltages V_display corresponding to the display data DATA_Write: A in nth through n+2nd frames, outputs the display data voltages V_display corresponding to the display data DATA_Write: B in an n+3rd frame, outputs the display data voltages V_display corresponding to the display data DATA_Write: C in n+4th through n+8th frames, and outputs the display data voltages V_display corresponding to the display data DATA_Write: D in an n+9th frame.
A frame T230 illustrated in FIG. 2B will now be described in detail with reference to FIG. 2C.
FIG. 2C is a timing diagram of a write indicating signal WRB, the display data DATA_Write, and the display data voltages V_display of the frame T230. Referring to FIG. 2C, the write indicating signal WRB is a signal indicating that the CPU sends the display data DATA to the display driver 230. A frame in which a write clock WCK is transmitted corresponds to a frame in which the display data DATA are transmitted. A frame in which the write indicating signal WRB maintains a predetermined level (e.g., a high level or a low level) corresponds to a frame in which the write clock WCK is not transmitted. The display data DATA_Write: WL1, WL2, WL3, . . . , WL(m−1), WLm, is written to the frame memory 233 in the frame in which the write clock WCK is transmitted.
When a frame includes m lines, WL1 is a first line of the display data DATA_Write written to the frame memory 233, WL2 is a second line of the display data DATA_Write written to the frame memory 233, . . . , and WLm is an mth line of the display data DATA_Write written to the frame memory 233. DL1 is a first line of the display data voltages V_display output by the scan driver 236, DL2 is a second line of the display data voltages V_display output by the scan driver 236, . . . , and DLm is an mth line of the display data voltages V_display output by the scan driver 236. Lines of the display data voltages V_display DL1, DL2, . . . , DLm are discriminated from each other by a horizontal blanking period (HBP). The display data voltages V_display of frames n FRAME, n+1 FRAME, etc., are discriminated from each other by a vertical blanking period (VBP).
However, referring to FIGS. 2A and 2B, because the display data DATA are sent and received in an asynchronous manner in the conventional asynchronous interface type, it is impossible to exactly predict when the display data DATA_Write will be written to the frame memory 233. In this case, it is impossible to reliably compare display data of a current frame with display data of a previous frame. Therefore, gray-level compensation processing technologies that essentially compare the display data of the current frame with the display data of the previous frame have not been applied to the conventional asynchronous interface type.